module mux_tb();
  reg [31:0] a0, a1;
  reg op;
  
  wire [31:0] out;
  
  mux dut(.a0(a0), .a1(a1), .op(op), .out(out));
  
  initial begin
    $dumpfile("muxwave.vcd");
    $dumpvars(0,mux_tb);
  end
  
  initial begin
    op = 0;    
    #10  op = 1;   
    #10  op = 0;
  end
  
  initial begin  
    a0 = $random;
    a1 = $random;
  end
  
endmodule